This DDR routing follows the controller spec’s layout guidelines.  The clock pairs and data lines are matched within 5mm at each SDRAM, while the control lines are 25mm longer and matched at each SDRAM as well.  Parts are on both the top and bottom sides — overlapping, so the bottom side silkscreen and pads are “hidden” in this view which shows four of the nine chips of this bank.  The tree-topology branches from the vias underneath the right side of the right pair of chips.

DDR SDRAM example...